Intel's FinFETs approach draws fire from rivals

Intel's FinFETs approach draws fire from rivals

SAN FRANCISCO – A panel of experts debated the future of semiconductor technology amid an array of new structures and materials, some trashing the FinFETs popularized by Intel. They made it clear there is no single road forward but rather a set of uncertain paths, each with its trade-offs.

“It’s clear planar silicon as we know it ends at about the 20-nm node, then there will be a race to different architectures and materials or combinations of both,” said Suresh Venkatesan, senior vice president of technology development at Globalfoundries, moderating an panel at the International Electron Devices Meeting (IEDM).

An IBM expert challenged that statement, showing a 10-nm planar process.

Panelists argued for an assortment of options including FinFETS, germanium, III-V materials, tunnel FETs, nanowires and fully depleted silicon-on-insulator. All sides agreed just what defines a new node is increasingly unclear.

“Any time we talk about new nodes, we should wash our mouths out with soap,” said Scott Thompson, chief technologist of startup SuVolta and a former Intel fellow. Engineers ignore traditional metrics, he added. “Intel’s 22 nm node is really 26 nm, so if Intel does new math, so will we."

“The next node after 14 nm will be some small number, but there’s no real pitch scaling,” Thompson added. “Pitch scaling will slow, but we will still have smaller number nodes anyway,” he said (see below).



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TAG:International Electron Devices Meeting III V Materials Tunnel FETs FinFETs IEDM Germanium Nanowires SOI