IBM demos racetrack memory and nanotech chips Electronics News

IBM introduced a number of research breakthrough at the IEEE International Electron Devices Meeting.

According to IBM, these advancements could lead to dramatically smaller, faster and more powerful computer chips, allowing the industry to surpass Moore’s Law.

With virtually all electronic equipment today built on complementary-symmetry metal–oxide–semiconductor (CMOS) technology, there is an urgent need for new materials and circuit architecture designs compatible with this engineering process as the technology industry nears physical scalability limits of the silicon transistor.  

IBM says it has successfully integrated the development and application of new materials and logic architectures on 200mm (eight inch) diameter wafers.

Racetrack Memory

Racetrack memory combines the benefits of magnetic hard drives and solid-state memory to overcome challenges of growing memory demands and shrinking devices.

IBM researchers are proving the feasibility of Racetrack memory by detailing the first of these sorts of devices integrated with CMOS technology on 200mm wafers.

They have demonstrated read and write functionality on an array of 256 in-plane, magnetized horizontal racetracks. Eventually, the density will be boosted using perpendicular magnetized racetracks and three-dimensional architectures.

Graphene

This first-ever CMOS-compatible graphene device can advance wireless communications, and enable new, high frequency devices, which can operate under adverse temperature and radiation conditions in areas such as security and medical applications.

The graphene integrated circuit, a frequency multiplier, is operational up to 5 GHz and stable up to 200 degrees Celcius. While detailed thermal stability still needs to be evaluated, these results are promising for graphene circuits to be used in high temperature environments.

New architecture flips the current graphene transistor structure on its head. Instead of trying to deposit gate dielectric on an inert graphene surface, the researchers developed a novel embedded gate structure that enables high device yield on a 200mm wafer.

Carbon Nanotubes

IBM researchers also demonstrated the first transistor with sub-10 nm channel lengths, which outperform the best of the comparable silicon-based devices currently in existence.

At channel lengths below 10nm, conventional silicon technology will face extreme performance difficulties even with new advanced device architectures.

The scaled carbon nanotube devices below 10nm gate length are a significant breakthrough for future applications in computing technology.

The carbon nanotube devices have improved switching speed in the on-state, as well as excellent off-state behaviour.

IBM demos racetrack memory and nanotech chips Electronics News