Mentor upgrades formal verification tools

Mentor upgrades formal verification tools

SAN JOSE, Calif. – Mentor Graphics enhanced its Questa tools, automating functions to expand coverage and ease use of formal verification techniques in chip design. The upgrade aims, in part, to get formal tools more broadly adopted.

A 2010 study said only 29 percent of chip designers have adopted formal tools. “There’s a huge growth opportunity for applying these techniques,” said Harry Foster, a chief scientist and formal verification expert at Mentor.

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Better test tools are certainly needed based on 2007 and 2010 surveys that both showed the fraction of chip design projects behind schedule remain at about 65 percent. About 70 percent of designs require re-spins, they both showed.

“You can totally miss a market window if a re-spin is needed,” said Foster noting the work can take more than three months and cost more than a million dollars.

Mentor’s new Questa CoverCheck automates the process of finding lines of code that cannot be formally verified. It also can show waveforms and generate output vectors for tests difficult to design. Alcatel-Lucent helped Mentor develop the code.

Separately, the latest version of Questa AutoCheck sports parallelism to run faster on multicore processors. The tool automates the process of finding common errors such as deadlocks and overflows often hard to detect in simulations.

Finally, Mentor expanded Questa CDC, a tool for finding problems due to clock domain crossing in SoCs that use IP blocks with separate asynchronous clocks. The new version improves performance five-fold in areas such as finding missing clock synchronizer blocks, Foster said.

“One of the biggest test issues emerging today is in SoC integration,” he said.

He noted a 53 percent growth from 2007-2010 in use of formal property checking. “The industry is being forced to mature based on more complex designs--what used to work on smaller designs doesn’t work,” he said.

“There’s been significant improvement in what we can handle--today formal tools handle hundreds of thousands of state elements--but it will never be enough so always need simulation, too,” said Foster.


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TAG:Formal Verification Mentor Graphics Harry Foster Formal Tools Mentor Questa CoverCheck AutoCheck SoCs Simulation Test EDA