IEDM targets next-gen memory technologies

IEDM targets next-gen memory technologies

This year’s International Electron Devices Meeting (IEDM) in San Francisco (Dec. 10-12) offers a mix futuristic academic research and evolutionary industrial technology approaching commercialization.

It’s no surprise that many interesting papers are related to non-volatile memory. It seems like there’s been a decades-long wait for flash to crash and a replacement technology emerging to pick up the pieces. As you might expect, this year's IEDM offers no shortage of papers related to emerging or "next generation" technologies. If you don't think 3-D NAND is the next generation, you can accuse me of ignoring new technology. But I think with 3-D stacking, flash will be its own replacement.

For those who think of emerging memory as an alphabet soup of RAMs, perhaps more interesting than any of the new technologies described in the IEDM papers might be the corporate dance that has been going on with the various floating-gate NAND replacements.

Since flash memory is ever approaching its demise, let’s start by looking at scaling. Both today's planar technology and future 3-D cells are covered in the joint Intel-Micron effort titled, "Scaling Directions for 2-D and 3-D NAND Cells."

What really caught my eye in the 2012 IEDM program was the number of presentations by Macronix. Perhaps best remembered as the company that helped spread video game titles to the masses via Nintendo, Macronix will present five IEDM papers on advanced semiconductor technology. Compare that total with a traditional powerhouse like STMicroelectronics with six or major flash player Hynix with three.

The first Macronix paper picks up on the theme of the invited paper. Macronix employed staircase contacts and a split-page bit line layout to produce an eight-layer 3-D NAND with vertical gate structures.

Another Macronix 3-D NAND paper. (“Design Innovations to Optimize the 3-D Stackable Vertical Gate (VG) NAND Flash,”) illustrates how many technologists see 3-D NAND in our near future.

Moving beyond memory, there are three papers related to CMOS platform technology that are definitely worth a look. First is IBM's 22-nm SOI technology with embedded DRAM. It's the first time dual stressors have been implemented adding Si:C for electron mobility enhancement in N-channel FETs along with the now commonplace SiGe source/drains for compressive strain-enhanced P-channel operation. If you don't think SOI technology with eDRAM is enough, IBM tops off their 22-nm platform with 15 levels of metal.

You’re probably thinking “Gaming." IBM probably is too.

Next: Foundry fate
TAG:International Electron Devices Meeting Don Scansen IEDM Memory