Business Imec integrates GermaniumTin into 10nm CMOS process

Business Imec integrates GermaniumTin into 10nm CMOS process

2013/09/18

Imec has developed a 10nm process integrating GermaniumTin (GeSn) to make depletion-mode junctionless mosfets.

The process, developed with partners KULeuven and AIST, is, says Imec: “An important step toward achieving tensile strain in MOSFET devices, and increasing their mobility.”

The researchers have been looking at integrating new materials into next generation CMOS devices to improve performance.

GeSn is a promising semiconductor candidate as channel material, due to its superior physical properties. GeSn enables increased switching speed of mosfets and can be used in fast optical communication.

While most prototype GeSn channel mosfets are fabricated on Ge substrates, silicon integration is preferred for CMOS compatibility.

However, epitaxial growth of GeSn on silicon substrates poses several challenges, including limited solubility of Sn in Ge (0.5%), its compositional fluctuations, Sn segregation, and large lattice mismatch (>4%). Therefore, it is critical to suppress these effects to obtain high performance devices with GeSn layers.

The researchers developed a solid phase epitaxy process, achieving ultrathin (>10µm) single-crystalline GeSn layers on silicon substrates showing tensile strain, attractive for strain engineering of Ge channels.

Furthermore, it reduces the difference between the direct and indirect band transition, resulting in acquisition of a direct band gap group IV material. Lastly, due to its non-equilibrium deposition conditions, the new method enables the development of GeSn with high Sn concentrations .

By decreasing the channel thickness with reactive ion etching (RIE) from ~30 to ~10 nm, the researchers improved the on/off ratio by more than one order of magnitude.

Additionally, hole depletion in the ultrathin (~10 nm) GeSn layers on silicon resulted in good transfer characteristics with an on/off ratio of 84.

Future research will focus on optimizing the GeS mosfet on silicon devices to further increase the channel mobility.

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