Embedded Systems Microchip adopts MIPS microAptive 32bit core

Embedded Systems Microchip adopts MIPS microAptive 32bit core

2013/11/18

Microchip has updated the MIPS processor within its 32bit PIC family, quadrupled memory, and release a tool which brings third-party firmware into the firm’s integrated development environment (IDE).

It has replaced the original M4K CPU with a MIPS microAptiv core, creating what will be known as PIC32MZ.

The firm is claiming 30% better code density, 330DMips and 3.28CoreMarks/MHz.

Adopting this core also brings with it 159 DSP instructions, to supporting streaming and digital audio.

Memory is up to 2Mbyte flash and 512kbyte RAM.

Peripherals will include a 28Msample/s ADC, crypto-engine, 480Mbit/s USB, 10/100 Ethernet and CANbus. A WQVGA display can be driven without an external graphics chip.

The firmware tool is called Harmony, and sits under the firm’s MPLAB IDE.

Within it, to minimise the chance of incompatibility, blocks are designed to communicate through a controlled abstraction layer and, according to product marketing manager Bill Hutchings, many combinations of blocks are pre-tested.

Dedicated to its 32bit parts, “this framework is the first to integrate the licensing, resale and support of Microchip and third-party middleware, drivers, libraries and real-time operating systems”, said Microchip. “Currently, Harmony includes third-party offerings from Interniche, freeRTOS, wolfSSL and OpenRTOS, with more on the way. The result is that developers can simplify their PIC32 MCU code development process by reducing common integration bugs, thus accelerating time to market.”

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