Taiwan embeds ReRAM in 28-nm process

Taiwan embeds ReRAM in 28-nm process

LONDON – The ability to embedding Resistive RAM (ReRAM) in a mainstream logic process could have major implications for the design of system-on-chip and foundry Taiwan Semiconductor Manufacturing Co. Ltd. is keeping tabs on the technology.

One of the more intriguing papers listed in the advance program for the 2012 International Electron Devices Meeting scheduled for Dec. 10 to 12 is from a research team from National Tsing-Hua University (Hsinchu, Taiwan) but with an additional affiliation to foundry chip maker TSMC(Hsinchu, Taiwan).

The paper (31.6) is entitled High-K metal gate contact RRAM (CRRAM) in pure 28-nm CMOS logic process. The extremely brief abstract states that a contact RRAM (CRRAM) cell has been realized in a HKMG 28-nm CMOS logic process without the use of any additional masking or process steps. This is done using a 35-nm by 35-nm contact hole.

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No more information is readily available regarding the paper but online searches reveals that the Tsing-Hua research team has previously worked with titanium-oxide based ReRAMs, typically in a TiN/TiON/SiO2 stacked arrangement sitting at the base of a tungsten contact plug attached to the drain of a conventional planar MOSFET.

The design is said to particularly compact compared with other types of ReRAM arrays and compatible with conventional logic manufacturing processes.

As recently as 2010 the team was working on a 1T-plus-1R ReRAM in 90-nm CMOS logic and claiming 1 million read-write cycle endurance.

The amount of memory included on system-chips is becoming increasingly large and responsible for much of the power consumption. The facility to hold data in dense non-volatile memory on a SoC – rather than in power consuming SRAM for even a few processor cycles – could drive power savings in leading-edge manufacturing.

The fact that the CRRAM can be implemented without any addition to the processing deck indicates a potentially easy introduction into chip manufacturing. However the fact that the IEDM paper is still essentially academic and written at the memory-cell level rather than at the array level indicates that more R&D is to be done. A demonstration or projection of considerably higher endurance would also be desirable.

Not only is the paper intriguing but it suggests a topic to watch out for at the International Solid States Circuits Conference in February 2012.


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TAG:National Tsing Hua University TSMC Hsinchu CRRAM semiconductor memory