Process showdown set for IEDM conference

Process showdown set for IEDM conference

LONDON – Chip giant Intel and the research partnership clustered around IBM and STMicroelectronics are each set to report progress in their various approaches to leading-edge IC manufacturing at the International Electron Devices Meeting in San Francisco in December.

Research teams are set to present on the FinFET approach--called tri-gate by Intel--on fully-depleted silicon-on-insulator (FDSOI) and on bulk planar processes at around 20-nm and beyond.

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Early in the proceedings (session 3.1), Intel is set to deliver a paper on its 22-nm FinFET technology for SoC applications. In the same session, a research team drawn from CEA-Leti, STMicroelectronics, IBM, Globalfoundries and Renesas will present a paper on ultra thin box and body (UTBB) FDSOI transistors for a multiple threshold voltage strategy at 20-nm and below.

Elsewhere in session 3.1, ST is set to report on switching energy efficiency in the UTTB process; IBM is set to present a 22-nm SOI process and Samsung researchers will report on the extensibility of its bulk 20-nm planar HKMG process.

Intel is already making processors using a 22-nm FinFET manufacturing process technology. But Intel now describes that process as a CPU process and has said it has not being optimized for lowest power consumption. Intel will provide engineering details of its 22-nm tri-gate SoC process and discuss its use of the approach to build a technology platform for SoC applications. That implies broad families of high-speed, low standby power and high voltage tolerant transistors, as well as RF and mixed-signal capabilities, according to the paper's abstract.

The high-speed logic transistors have sub-threshold leakages ranging from 100-nA per micron to 1-nA per micron, while the low-power versions feature a leakage of less than 50-pA per micron. Nonetheless, the process retains 1.8- and 3.3-volt transistors for analog circuits, and legacy circuits.

The Intel 22-nm SoC platform also includes carbon-doped oxide interconnect and three different types of SRAM bit cell to provide options between density, performance and low voltage operation, the abstract states.

In another session (session 18) on Dec. 11, a paper authored by a team from IBM, STMicroelectronics, Globalfoundries, Renesas, Soitec and CEA-Leti will report on another SOI process at 22-nm known as ETSOI for extremely thin silicon-on-insulator. This process has a silicon channel for n-type transistors and strained silicon-germanium channel for p-type transistors.

IEDM is set to take place Dec. 10 to 12 at the Hilton San Francisco Union Square.


Related links and articles:

• IEDM

News articles:

• Globalfoundries looks to leapfrog fab rivals
• Intel describes 22-nm SoC process, not chips
• Intel’s Haswell boosts battery life, graphics

TAG:Intel IBM STMicroelectronics Renesas Globalfoundries